Dynamic voltage scaling is known and is an approach whereby power dissipation in digital hardware, e.g., microprocessors, etc., can be limited. As is known power dissipation of CMOS and similar semiconductor technologies increases with switching frequencies (clock frequencies) as well as power supply voltage. On the other hand, processing capacities increase with increased switching frequency and this may require increased supply voltages.
Thus, an increase in power supply voltage may be required to increase a processor or other switching core clock frequency. Minimizing power dissipation requires that the supply voltage closely match the voltage that is required to accommodate the switching frequency that is needed to handle present processing loads.
Some prior art systems use an open loop system to control the DVSI. Open loop systems normally have to be operated conservatively (lots of margin) in order to account for worst case process and temperature variations. This typically results in significant power dissipation over an otherwise optimized system.
Closed loop systems in theory could compensate for the process and temperature variations. Embodiments of prior art closed loop DVSI control systems have suffered from undue latency between a recognition that power supply voltage should or could be adjusted and thus, undue dissipation occurs or processing latencies suffer.